
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.0 12
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(T
CASE
= 0 °C ~ 85 °C; V
DDQ
= 1.8V ± 0.1V; V
DD
= 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)
Clock Cycle Time (Average)
CK high-level width (Average)
CK low-level width (Average)
Write command to DQS associated clock edge
Write command to 1
st
DQS latching transition
DQS falling edge to CK setup time (write cycle)
DQS falling edge hold time from CK (write cycle)
DQS input low (high) pulse width (write cycle)
Address and control input setup time
Address and control input hold time
DQ and DM input setup time (differential data
strobe)
DQ and DM input hold time(differential data
strobe)
DQ and DM input pulse width (each input)
DQ output access time from CK/
DQS output access time from CK/
Data-out high-impedance time from CK/
DQS low-impedance time from CK/
DQ low-impedance time from CK/
DQS-DQ skew (DQS & associated DQ signals)
Minimum half clk period for any given cycle;
defined by clk high (Tch) or clk low (Tcl) time
Data output hold time from DQS
Active bank A to Active bank B command
Four Activate Window for 1KB page size
products
Write recovery time without Auto-Precharge
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a Non-read command
Exit self refresh to a Read command
Exit precharge power down to any Non- read
command
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