Elixir M2Y2G64CB8HC5N-CG Ficha de datos descargar pdf

M2Y2G64CB8HC5N / M2Y2G64CB8HC9N

2GB: 256M x 64

Unbuffered DDR3 SDRAM DIMM

REV 1.1 1

01/2010

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

240pin Unbuffered DDR3 SDRAM MODULE

Based on 128Mx8 DDR3 SDRAM C Die

Features

• Performance:

• JEDEC Standard 240-pin Dual In-Line Memory Module

• 256Mx64 DDR3 Unbuffered DIMM based on 128Mx8 DDR3

Elixir SDRAM

• Intended for 533MHz and 667MHz applications

• Inputs and outputs are SSTL15 compatible

• V

= V

DDQ

= 1.5Volt ± 0.075Volt

• SDRAMs have 8 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

• 8 bit pre-fetch

• Two different termination values (Rtt_Nom & Rtt_WR)

• Extended operating temperature rage

• Auto Self-Refresh option

• Automatic and controlled precharge commands

• Programmable Operation:

- DIMM  Latency: 6,7,8,9,

- Burst Type: Sequential & Interleave

- Burst Length: BC4, BL8

- Operation: Burst Read and Write

• 14/10/2 Addressing (row/column/rank) – 2GB

• Serial Presence Detect

• Gold contacts

• SDRAMs in 78 BGA Package

• RoHS compliance

Description

M2Y2G64CB8HC5N and M2Y2G64CB8HC9N are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line

Memory Module (UDIMM), two ranks 256Mx64 high-speed memory array. M2Y2G64CB8HC5N and M2Y2G64CB8HC9N use sixteen

128Mx8 DDR3 SDRAMs. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The

use of these common design files minimizes electrical variation between suppliers. All Elixir DDR3 SDRAM DIMMs provide a

high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.

The DIMM is intended for use in applications operating up to 533 MHz or 667MHz clock speeds and achieves high-speed data transfer

rates of up to 1066Mbps or 1333 Mbps. Prior to any access operation, the device  latency and burst / length / operation type must be

programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1, and BA2 are using for the mode register set cycle.

The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of

serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.

Speed Sort

PC3-8500

PC3-10600

Unit

-BE

-CG

DIMM  Latency

Clock Frequency

533

667

MHz

Clock Cycle

1.875

1.5

DQ Burst Frequency

1066

1333

Mbps

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