Elixir M2Y1GH64TU8HD6B-AC Ficha de datos descargar pdf

M2Y51H64TU88D0B / M2Y51H64TU88D6B / M2Y1GH64TU8HD0B / M2Y1GH64TU8HD6B

512MB: 64M x 64 / 1GB: 128M x 64

Unbuffered DDR2 SDRAM DIMM Preliminary Edition

REV 0.1 1

08/2008

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

240pin Unbuffered DDR2 SDRAM MODULE

Based on 64Mx8 DDR2 SDRAM D Die

Features

• Performance:

Speed Sort

PC2-5300

PC2-6400

Unit

-3C

-AC

DIMM  Latency

f CK

Clock Frequency

333

400

MHz

t CK

Clock Cycle

2.5

f DQ

DQ Burst Frequency

667

800

MHz

• JEDEC Standard 240-pin Dual In-Line Memory Module

• 64Mx64 and 128Mx64 DDR2 Unbuffered DIMM based on

64Mx8 DDR2 SDRAM D die

• Intended for 333MHz, and 400MHz applications

• Inputs and outputs are SSTL-18 compatible

• V

= V

DDQ

= 1.8V ± 0.1V

• SDRAMs have 4 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

• Bi-directional data strobe with one clock cycle preamble and

one-half clock post-amble

• Address and control signals are fully synchronous to positive

clock edge

• Programmable Operation:

- Device  Latency: 3, 4, 5

- Burst Type: Sequential or Interleave

- Burst Length: 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 14/10/1 Addressing (row/column/rank) – 512MB

• 14/10/2 Addressing (row/column/rank) – 1GB

• 7.8 µs Max. Average Periodic Refresh Interval

• Serial Presence Detect

• Gold contacts

• SDRAMs in 60 ball BGA Package

• RoHS compliance

Description

M2Y51H64TU88D0B, M2Y1GH64TU8HD0B, M2Y51H64TU88D6B and M2Y1GH64TU8HD6B are 240-Pin Double Data Rate 2 (DDR2)

Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as one-rank 64Mx64 and two ranks 128Mx64

high-speed memory array. M2Y51H64TU88D0B and M2Y51H64TU88D6B use eight 64Mx8 DDR2 SDRAMs. M2Y1GH64TU8HD0B and

M2Y1GH64TU8HD6B use sixteen 64Mx8 DDR2 SDRAMs. These DIMMs are manufactured using raw cards developed for broad

industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All Elixir

DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.

The DIMM is intended for use in applications operating up to 333MHz and 400MHz clock speeds and achieves high-speed data transfer

rates of up to 667MHz and 800MHz. Prior to any access operation, the device  latency and burst / length / operation type must be

programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.

The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of

serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.

1 2 3 4 5 6 ... 17 18