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M2Y51H64TU88D0B / M2Y51H64TU88D6B / M2Y1GH64TU8HD0B / M2Y1GH64TU8HD6B

512MB: 64M x 64 / 1GB: 128M x 64

Unbuffered DDR2 SDRAM DIMM Preliminary Edition

REV 0.1 9

08/2008

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Serial Presence Detect – Part 1 of 2 (1GB)

128Mx64 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 1.8V DDR2 SDRAMs with SPD

Byte

Description

SPD Entry Value

Serial PD Data Entry

(Hexadecimal)

Note

-3C

-AC

-3C

-AC

Number of Serial PD Bytes Written during Production

128

Total Number of Bytes in Serial PD device

256

Fundamental Memory Type

DDR2 SDRAM

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

Number of DIMM Ranks

2 ranks, Height=30mm

Data Width of Assembly

X64

Reserved

Undefined

Voltage Interface Level of this Assembly

SSTL_1.8V

DDR2 SDRAM Device Cycle Time at CL=X

2.5

DDR2 SDRAM Device Access Time from Clock at CL=X

0.45

0.40

DIMM Configuration Type

Non parity/ECC

Refresh Rate/Type

7.8μs/self

Primary DDR2 SDRAM Width

Error Checking DDR2 SDRAM Device Width

Undefined

Reserved

Undefined

DDR2 SDRAM Device Attributes: Burst Length Supported

4,8

DDR2 SDRAM Device Attributes: Number of Device Banks

DDR2 SDRAM Device Attributes: CAS Latencies Supported

3,4,5

DIMM Mechanical Characteristics

<4.1(mm)

DDR2 SDRAM DIMM Type Information

Regular UDIMM (133.35mm)

DDR2 SDRAM Module Attributes:

Normal DIMM

DDR2 SDRAM Device Attributes: General

Support weak Driver,

50Ω ODT, and PASR

Minimum Clock Cycle at CL=X-1

3.75ns

Maximum Data Access Time from Clock at CL=X-1

0.5ns

Minimum Clock Cycle Time at CL=X-2

5.0ns

Maximum Data Access Time from Clock at CL=X-2

0.6ns

Minimum Row Precharge Time (t

)

15ns

12.5ns

Minimum Row Active to Row Active delay (t

RRD

)

7.5ns

Minimum RAS to CAS delay (t

RCD

)

15ns

12.5ns

Minimum RAS Pulse Width (t

RAS

)

45ns

Module Bank Density

512MB

Address and Command Setup Time Before Clock (t

)

0.2ns

0.17ns

Address and Command Hold Time After Clock (t

)

0.27ns

0.25ns

Data Input Setup Time Before Clock (t

)

0.10ns

0.05ns

Data Input Hold Time After Clock (t

)

0.17ns

0.12ns

Write Recovery Time (t

)

15ns

Internal Write to Read Command delay (t

WTR

)

7.5ns

Internal Read to Precharge delay (t

RTP

)

7.5ns

Reserved

Undefined

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 17 18

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