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M2S4G64CB88B5N / M2S8G64CB8HB5N
4GB: 512M x 64 / 8GB: 1024M x 64
PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
REV 1.0 20
06/2012
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
Timing of RD/RDA command to Power Down entry
tRDPDEN
tRDPDENmin.: RL+4+1
tRDPDENmax.: -
nCK
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRPDENmin.: WL + 4 + (tWR / tCK(avg))
tWRPDENmax.: -
nCK
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRAPDEN
tWRAPDENmin.: WL+4+WR+1
tWRAPDENmax.: -
nCK
Timing of WR command to Power Down entry (BC4MRS)
tWRPDEN
tWRPDENmin.: WL + 2 + (tWR / tCK(avg))tWRPDENmax.: -
nCK
Timing of WRA command to Power Down entry
(BC4MRS)
tWRAPDEN
tWRAPDENmin.: WL + 2 +WR + 1
tWRAPDENmax.: -
nCK
Timing of REF command to Power Down entry
tREFPDEN
tREFPDENmin.: 1
tREFPDENmax.: -
nCK
Timing of MRS command to Power Down entry
tMRSPDEN
tMRSPDENmin.: tMOD(min)
tMRSPDENmax.: -
ODT Timings
ODT high time without write command or
with write command and BC4
ODTH4
ODTH4min.: 4
ODTH4max.: -
nCK
ODT high time with Write command and BL8
ODTH8
ODTH8min.: 6
ODTH8max.: -
nCK
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
tAONPD
2
8.5
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
tAOFPD
2
8.5
ns
RTT turn-on
tAON
-225
225
ps
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
tAOF
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
tCK(avg)
Write Leveling Timings
First DQS/DQS# rising edge after
write leveling mode is programmed
tWLMRD
40
-
nCK
DQS/DQS# delay after write leveling mode is programmed
tWLDQSEN
25
-
nCK
Write leveling setup time from rising CK, CK#
crossing to rising DQS, DQS# crossing
tWLS
165
-
ps
Write leveling hold time from rising DQS, DQS#
crossing to rising CK, CK# crossing
tWLH
165
-
ps
Write leveling output delay
tWLO
0
7.5
ns
Write leveling output error
tWLOE
0
2
ns
- , , 4
- RefCA(DC) 8
- RefDQ(DC) 8
- 06/2012 12
- Detail A Detail B 21
- Units: Millimeters (Inches) 21
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